Electric power dissipation in advanced ICs (integrated circuits) has become critical for a number of reasons. Consumer electronics used in battery-operated devices may have a requirement to minimize power to prolong battery life. Excessive power consumption in other complex ICs can cause heat dissipation issues requiring special cooling infrastructure that adds to the system cost. Hence various IC design techniques are commonly used to limit the power consumed during normal operation of the chip, such as clock gating, dynamic voltage and frequency scaling (DVFS), and power shut-off (PSO).
This invention relates to design, testing and simulation of semiconductor devices including testing of integrated circuits (chips). The electric power rails (conductors) in the chip are normally designed, per the chip specification, for maximum power dissipation during functional operation mode (the actual IC use). However, during manufacturing test of the IC/die/wafer, the various power saving techniques employed in the chip under test may be turned off to enable full chip testing. For example, clock gating logic may be disabled and bypassed, and the chip's power-shut-off logic may be disabled to allow full chip test at system frequency for delay testing. ATPG (automatic test pattern generation) scan test patterns (the applied test signals, also known as test vectors) generally lead to much more switching in the IC than during the functional mode, especially during the scan shift operation, due to the way most ATPG tools (software) create test patterns. As a result, the chip may undesirably exceed its limit of power consumption (either average or instantaneous) during manufacturing test.
It is common practice to lower the test clock frequency during scan shift operation to help reduce average power consumption. However, since all test scan registers on-chip more or less shift (switch) simultaneously during scan shift operation, the instantaneous peak electric current drawn may still exceed the limit of the power rails and result in signal and power integrity issues, such as ground bounce and power variation, dI/dt (change of current over time) threshold exceeded, etc. This can invalidate the test and lead to test failure, affecting the manufacturing yield. Power consumption during manufacturing test of digital integrated chips (IC's) thus is an important consideration. Due to high switching activity during scan based manufacturing test, the power consumption may exceed the thermal limit or power-supply limit of the chip-causing failure of the test due to ground-bounce or other related issues, or even premature failure of the chip due to excessive heat generation.